1. Field of the Invention
The present invention relates to an electronic instrument having a semiconductor memory device for which read and write operations are executed in synchronism with strobe signals, and the semiconductor memory device.
2. Description of the Related Art
A circuit configuration of a part of a conventional electronic instrument is shown in FIG. 1. Referring to FIG. 1, there is a DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) 1 which operates in synchronism with rising and falling edges of a clock signal. The actual electronic instrument has a plurality of DDR-SDRAMs and a control chip controlling the plurality of DDR-SDRAMs.
The electronic instrument further has a positive-phase clock line 2, an inverse-phase clock line 3, a command bus 4, an address bus 5 and a data bus 6. A positive-phase clock signal CLK is transmitted through the positive-phase clock line 2. An inverse-phase clock signal /CLK having a phase which is in inverse relation to the phase of the positive-phase clock signal CLK is transmitted through the inverse-phase clock line 3. Command signals are transmitted through the command bus 4. Row address signals and column address signals are transmitted through the address bus 5. Data is transmitted through the data bus 6.
In addition, a strobe signal line 7 is provided in the electronic instrument. An output strobe signal QSOUT is transmitted to the control chip through the strobe signal line 7 in a data read operation (a data output operation) for each of the plurality of DDR-SDRAMS (e.g., the DDR-SDRAM 1). The output strobe signal QSOUT is supplied to the control chip together with output data DQOUT and used to appoint a take-in timing of the output data DQOUT. An input strobe signal QSIN is transmitted to the DDR-SDRAM 1 through the strobe signal line 7 in a data write operation (a data input operation) for the DDR-SDRAM 1. The input strobe signal QSIN is supplied to the DDR-SDRAM 1 together with input data DQIN and used to appoint a take-in timing of the input data DQIN.
An essential part of the DDR-SDRAM 1 is shown in FIG. 2. Referring to FIG. 2, the DDR-SDRAM 1 has a command buffer 9, a command decoder 10 and a controller 11. The command buffer 9 receives a command signal transmitted through the command bus 4. The command decoder 10 decodes the command signal output from the command buffer 9. The controller 11 receives a decoded command signal from the command decoder 10 and controls an internal circuit of the DDR-SDRAM 1 in accordance with the contents of the decoded command signal.
The DDR-SDRAM 1 further has an address buffer 12, a plurality of memory banks 14-1-14-m and address latches 13-1-13-m. The address buffer 12 receives a row address signal and a column address signal transmitted through the address bus 5. Each of the address latches 13-1-13-m latches the row address signal and column address signal output from the address buffer 12. The memory bank 14-1 has a memory array 15-1 in which memory cells are arranged, a row decoder 16-1, a sense-amp unit 17-1 and a column decoder 18-1. The row decoder 16-1 decodes the row address signal latched by the address latch 13-1 to select a ward line. The sense-amp unit 17-1 includes sense amplifiers amplify data read out from a memory cell specified by the selected word line. The column decoder 18-1 decodes the column address signal latched by the address latch 13-1 to select a column. The other memory banks (14-m) have the same structure as the memory bank 14-1.
The DDR-SDRAM 1 has data bus buffers 19-1-19-m and write buffers 20-1-20-m. Each of the data bus buffers 19-1-19-m amplifies read data output from a corresponding one of the memory banks 14-1-14-m to a corresponding one of core data buses CDB1-CDBm. Each of the write buffers 20-1-20-m outputs write data to a corresponding one of the core data buses CDB1-CDBm.
The DDR-SDRAM 1 further has a data output buffer 21, a data input buffer 22, a strobe output buffer 23 and a strobe input buffer 24. A peripheral data bus DB connects the data bus buffers 19-1-19-m and the write buffers 20-1-20-m to the data output buffer 21 and the data input buffer 22. The data output buffer 21 outputs the output data DQOUT to the outside and the data input buffer 22 receives from the outside input data DQIN having N bits arranged in parallel. The strobe output buffer 23 outputs the output strobe signal QSOUT. The strobe input buffer 24 receives the input strobe signal QSIN and is used to control a take-in timing of the input data DQIN.
Relationships among the complementary clock signals CLK and /CLK, the output strobe signal QSOUT and the output data DQOUT in the data output operation (the data read operation) for the DDR-SDRAM 1 are shown in FIG. 3. Referring to FIG. 3, a time tCKQS is a QS access time from an edge of the clock signal CLK, and a time tQSPRE is a QS preamble time, a time tQSPOT is a QS postamble time. Further, a time tQSQ is a data output skew from an edge of the output strobe signal QSOUT, a time tAC is a data access time from an edge of the output strobe signal QSOUT, and a time tDV is a data output valid time.
Relationships among the complementary clock signals CLK and /CLK, the input strobe signal QSIN and the input data DQIN in a data input operation (the data write operation) for the DDR-SDRAM 1 are shown in FIG. 4. Referring to FIG. 4, a time tDS is a data input set up time, and a time tDH is a data input hold time from each edge of the input strobe signal QSIN.
In the electronic instrument having the above structure, the output strobe signal QSOUT is transmitted from the DDR-SDRAM 1 through the strobe signal line 7 together with the output data DQOUT through the data bus 6 so that the settling period for the output data DQOUT on the basis of the output strobe signal QSOUT is constant. As a result, it is easy for the control chip to receive the output data DQOUT. The input strobe signal QSIN is transmitted from the control chip through the strobe signal line 7 together with the input data DQIN through the data bus 6 so that the settling period the input data DQIN on the basis of the input strobe signal QSIN is constant. As a result, it is easy for the DDR-SDRAM 1 to receive the input data DQIN.
However, if the rising time and falling time of each of the strobe signals QSOUT and QSIN are varied, the strobe period is not constant. The settling period for the data DQOUT and DQIN is thus not constant. As a result, it is difficult to adjust the take-in timing of the data DQOUT and DQIN. If the strobe period is shortened to access the DDR-SDRAM 1 at a very high speed, for example, if the strobe period is equal to or less than 4 nanoseconds (ns), the data DQOUT and DQIN may not be certainly settled.